One question from the chatroom was, does the FPGA loose it’s programmed configuration on power off. Essentially, no.
The Fispy FPGA has, “Instant-on configuration from internal Flash PROM” and “powers up in milliseconds”.
So when you create a .jed file, and upload the configuration to the FPGA, it is stored in internal Flash PROM. When you power off then on the Fipsy FPGA, within a few milliseconds the FPGA is restored to it’s starting programmed configuration. If you had any state information stored in operating registers, those may be lost, as all information and registers are restored to the initial configuration state.
Keep in mind that MOST fpga’s don’t have this convenient configuration storing-capacity built into the chip. The configuration is often stored in memory of a nearby component, and loaded at power up. Note that the MachXO2 chip used in the Fipsy FPGA also, “Optional dual boot with external SPI memory” meaning you can still load in a configuration externally, as is more conventional.