Learn Verilog Syntax

This is the Syntax guide. Please absorb it. It’s not perfect, but this is an under-developed topic.

Introduction to Verilog http://www.doe.carleton.ca/~shams/ELEC3500/PetervrlK.pdf

Note that Verilog is robust, and includes syntax that is “synthesizable” and “non-synthesizable”. The idea is that, you can use software to model what would happen to the design if it could theoretically be uploaded to the FPGA. You can write tests and mimic outside-world interactions with the device. You can then monitor signals and outputs over time with modeling software. For instance, you can have a delay of an assignment, so after 50 clock-ticks, an input signal turns on – mimicking  a signal coming into the device, like pushing a button. However, the syntax for a delay, as seen here, is not synethsizable

initial begin

#0 signal = 0;
#50 signal = 1;


What that code says is set signal = 0 at time 0 (#0) and after 50 clock ticks (#50) set it to 1. That syntax is valid Verilog, but it is not synthesizable, meaning you can’t turn it into a true physical configuration on the FGPA.  The purpose of it is to be part of a test bench that is used during modeling. In the above guide, you can defer learning about non-synthesizable syntax until you are ready to begin testing designs.

Additional Learning Guides

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